During test mode, switching activity in scan-chain integrated circuits increase. As a result, the peak and average power dissipation in test mode often become higher than the normal mode. This can result in yield loss, heat damage to the circuit under test (CUT), and structural damage as well. In this paper, a new technique has been proposed that can efficiently reorder the test vectors targeting low switching activity in the scan chain. The technique has been verified with ISCAS'89 benchmark circuits. The achieved reduction in switching activity goes up to 12% when compared to the pattern order generated by an automatic test pattern generator (ATPG) tools like ATALANTA.