Three-dimensional integrated circuit (3D IC) is an emerging field with huge prospects. It provides significant benefits over conventional 2D IC. However, testing of 3D ICs is quite challenging compared to conventional 2D ICs due to constrained access to the cores and high power density. This work presents a test scheduling algorithm for 3D ICs to minimize test time. The peak power of the generated schedule is also considered and optimized to balance with test time using a weighted cost function. TSV limit is also considered to check test resource cost. The proposed algorithm applied on different ITC'02 benchmark circuits shows promising results.