The globalised nature of design and manufacturing process of Integrated Circuits (ICs) makes them susceptible to malicious alterations called Hardware Trojan Horses (HTH). Prior estimation of degree of vulnerability of internal nets of an IC is therefore a valuable measure to ensure its security. An improved testability measurement process has been suggested by this paper, which effectively assesses the vulnerability of the internal nets to HTH insertion. The evaluated vulnerability measures can be used to generate test patterns, which in turn helps detect the presence of HTH in the IC.