Abstract:
In this paper, a low area and high speed SHA-1 implementation with multi-input addition based on a carry-save adder is proposed. Compared with the fastest SHA-1 design up...Show MoreMetadata
Abstract:
In this paper, a low area and high speed SHA-1 implementation with multi-input addition based on a carry-save adder is proposed. Compared with the fastest SHA-1 design up to date, our implementation reduces the area by 24.5% as well as increases the speed by 13.6%. When the proposed scheme keeps the same clock frequency as the counterpart, it decreases the area by 39.7% further.
Published in: 2011 International SoC Design Conference
Date of Conference: 17-18 November 2011
Date Added to IEEE Xplore: 26 January 2012
ISBN Information: