Low area and high speed SHA-1 implementation | IEEE Conference Publication | IEEE Xplore

Low area and high speed SHA-1 implementation


Abstract:

In this paper, a low area and high speed SHA-1 implementation with multi-input addition based on a carry-save adder is proposed. Compared with the fastest SHA-1 design up...Show More

Abstract:

In this paper, a low area and high speed SHA-1 implementation with multi-input addition based on a carry-save adder is proposed. Compared with the fastest SHA-1 design up to date, our implementation reduces the area by 24.5% as well as increases the speed by 13.6%. When the proposed scheme keeps the same clock frequency as the counterpart, it decreases the area by 39.7% further.
Date of Conference: 17-18 November 2011
Date Added to IEEE Xplore: 26 January 2012
ISBN Information:
Conference Location: Jeju, Korea (South)

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