Spin-transfer torque RAM (STT-RAM)-based main memory can suffer from a security problem due to its non-volatility. Data encryption, which can be applied to resolve this problem, can give significant performance degradation due to the additional latency of decryption/encryption in main memory accesses. We propose an STT-RAM architecture where two regions have different retention times. A small short retention-time region, which works as a write-through cache, keeps data unencrypted thereby avoiding the additional latency. The short retention time also makes the memory chip secure by decaying data fast in case of sudden power off. The large long retention-time region contains the original version of main memory data in the encrypted form thereby providing full security. Experimental results, with SPEC2006 benchmarks, show that the proposed method offers 17.1%~36.3% improvement in memory access latency. For 10 memory-intensive programs, we can obtain average 15.3% improvement in total execution cycles.