Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor. Our proposed ternary ALU demonstrates improved energy-efficiency compared to the binary design; 87% and 93% reduction of power-delay product in the 5- trit ternary adder-subtractor and ternary multiplier, respectively.