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Bit-Serial multiplier based Neural Processing Element with Approximate adder tree | IEEE Conference Publication | IEEE Xplore

Bit-Serial multiplier based Neural Processing Element with Approximate adder tree


Abstract:

Deep learning algorithms are computationally intensive and require dedicated hardware accelerators. Deep learning algorithms repeat multiply-accumulate (MAC) operations. ...Show More

Abstract:

Deep learning algorithms are computationally intensive and require dedicated hardware accelerators. Deep learning algorithms repeat multiply-accumulate (MAC) operations. This process produces a large number of partial sums that account for about 60% of the total logic. Therefore, optimizing multi-operand adders (MOA) that add these partial sums can reduce the high resource utilization of deep learning accelerators. This study designed a neural processing element with approximate adders that reduces resource utilization without changing the accuracy of deep learning algorithms by using the fault tolerance property of deep learning algorithms. As a result, the accuracy dropped by only 0.04% with 4.7% less resource usage.
Date of Conference: 21-24 October 2020
Date Added to IEEE Xplore: 01 February 2021
ISBN Information:
Print on Demand(PoD) ISSN: 2163-9612
Conference Location: Yeosu, Korea (South)

Funding Agency:


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