For an efficient data transmission between logic die and core die in HBM DRAM, Through-Silicon-Via (TSV) is an essential part that connects stacked memories. TSV is a vertical component which cannot be found in the conventional 2D memory. It plays an important role in improving integration in 3D memory structure. However, due to its temporal variation and technological weakness, error cases occur frequently in TSV. Following this, to increase the reliability of the memory operation, fault detection and correction method for TSV is a new challenge in 3D memory. For the efficient fault correction, fault detection method that classifies hard fault and soft error has been studied. In this paper, a new TSV fault detection method using error pattern analysis will be presented. As a result, the proposed scheme shows higher detection success rate with low area overhead, compared to the conventional scheme.