SRAM-based In-Memory-Computing (IMC) for processing multiply-accumulate (MAC) operations is one of the promising techniques to overcome von-Neumann Bottleneck. The SRAM-based IMC generally requires multi-bit input activation to achieve a high inference accuracy. In this paper, a charge-sharing based 10T SRAM IMC architecture is proposed which can process multibit inputs on cell array by employing bit-line parasitic capacitances without Digital to Analog Converter (DAC). The proposed DAC-less multi-bit IMC can efficiently reduce computing energy without latency overhead. The hardware implementation with 28nm CMOS process shows that the proposed SRAM based IMC macro achieves 10.1TOPS/W with 7ns inference time at 1V and 91.4% CIFAR-10 inference accuracy.