Loading [a11y]/accessibility-menu.js
Toward Heterogeneous Virtual Platforms For Early SW Development | IEEE Conference Publication | IEEE Xplore

Toward Heterogeneous Virtual Platforms For Early SW Development


Abstract:

Virtual platform (VP) has been used for early software (SW) development to shorten the product release period. However, due to the large size of system-on-a-chip (SoC) in...Show More

Abstract:

Virtual platform (VP) has been used for early software (SW) development to shorten the product release period. However, due to the large size of system-on-a-chip (SoC) in recent days, it is difficult to make a VP that models the whole SoC in time. Thus, a SoC is divided into many sub-systems and VPs are developed with respect to them. However, SW code developed with a VP for a sub-system may have potential faults since the code is not fully tested with a whole SoC environment. In this paper, we introduce a solution that integrates two heterogeneous VPs, each of which has a different simulator to each other. For that, a shared memory-based inter-process communication (IPC) is proposed to communicate data within the two different VPs. In addition, we evaluate two core-grouping structures in the view of simulation performance and stability, which is shown in the experimental results. In industry, using the proposed methods (i.e., IPC technique, core-grouping), VPs, which are developed with its own simulation environment, can be integrated so that all the SW codes can be tested in the whole SoC environment.
Date of Conference: 19-22 October 2022
Date Added to IEEE Xplore: 07 February 2023
ISBN Information:
Print on Demand(PoD) ISSN: 2163-9612
Conference Location: Gangneung-si, Korea, Republic of

References

References is not available for this document.