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Exploring the high-throughput and low-delay hardware design of SM4 on FPGA | IEEE Conference Publication | IEEE Xplore

Exploring the high-throughput and low-delay hardware design of SM4 on FPGA


Abstract:

SM4 (or SMS4) is a 32-round unbalanced Feistel block cipher. This paper explores the hardware design method of SM4 for different scenarios on FPGA. Targeting the real-tim...Show More

Abstract:

SM4 (or SMS4) is a 32-round unbalanced Feistel block cipher. This paper explores the hardware design method of SM4 for different scenarios on FPGA. Targeting the real-time high speed communication system on FPGA, we construct the pipeline across the unrolled rounds to gain balanced pipeline stages with online and offline key expansion schemeS. Meanwhile, for the low-delay application scenario, various SM4 structures are implemented to show the trade-off relationship between the number of unrolled rounds and the performance metrics. The experimental results show that in the high-throughput application scenario, our optimization method can achieve a throughput of 118. 19\text{Gbps} with relatively higher efficiency (\text{Mbps}/\text{area}); in the low-delay application scenario, the delay \times area can be minimized to 177.18 ns \times(\text{FF}+ \text{LUT}) when unfolding 2 rounds of operations.
Date of Conference: 19-22 October 2022
Date Added to IEEE Xplore: 07 February 2023
ISBN Information:
Print on Demand(PoD) ISSN: 2163-9612
Conference Location: Gangneung-si, Korea, Republic of

References

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