Current and next generation WLAN devices have an increasing need for processing power to support new WLAN features that require high computation complexity. In this paper, we present our design for an 802.11ac/ax system with an application specific instruction-set processor (ASIP) to implement multiple disjoint system tasks at much faster speed compared to a general purpose processor. As a proof of concept, we implemented the channel SVD, channel compression/decompression and beam-forming weight computations at the same time in the embedded ASIP core to support the 802.11ac MU-MIMO beamforming feature. In addition, the design was synthesized in the Zynq zc706 evaluation board programmable logic (PL) along with the rest of the PHY. The actual task to be done by the ASIP core at any given time can be programmed via the zc706 processing system (PS) resulting in a very high hardware savings compared to an all hardware implementation.