In this paper we develop a fast approach to analyze the total leakage power of a large circuit block, considering both gate leakage, I/sub gate/, and subthreshold leakage, I/sub sub/. The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies. We propose simple and accurate heuristics to quickly estimate the state-dependent total leakage current considering the interaction between I/sub sub/ and I/sub gate/. We apply this method to ISCAS benchmark circuits in a projected 100 nm technology and demonstrate excellent accuracy compared to SPICE simulation with a 20,000X speedup on average.