The aggressive scaling of CMOS process is central to the continued performance enhancement of microprocessors. While the process scales every generation the I/O interface standards do not change at the same rate. This introduces a host of reliability issues. One not only needs to design for performance, but should also meet the reliability goals in the scaled technology for these standards. This paper presents a 3.3 V I/O buffer designed using 1.8 V transistors in a 65 nm bulk CMOS process. Proposed I/O uses a novel differential amplifier based pre-driver topology, which has excellent gate-oxide reliability, runs at 200 MHz and has comparative area and static power of an equivalent I/O in 65 nm 3.3 V CMOS process.