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Analysis of power supply induced jitter in actively de-skewed multi-core systems | IEEE Conference Publication | IEEE Xplore

Analysis of power supply induced jitter in actively de-skewed multi-core systems


Abstract:

This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and po...Show More

Abstract:

This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power supply variation in multi-core designs. Using the methodology, we compare four different de-skewing topologies (region-based, linear, ring, and a tree) for nominal performance and robustness to power supply variation. We conclude that under nominal conditions, the ring and line topologies are better with a large number of cores, but, when power supply is considered, the region topology is best.
Date of Conference: 22-24 March 2010
Date Added to IEEE Xplore: 15 April 2010
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Conference Location: San Jose, CA, USA

References

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