A simple array-based test structure has been developed to characterize AC variability in deeply scaled MOSFETs. Each test structure consists of 128 devices under test (DUTs) whose relative delays are characterized using a logic gate-based delay detector circuit. The delay measurement technique only requires a single off-chip DC voltage measurement for each DUT. A design-time optimization is performed on each DUT array to ensure that the measured delays of each DUT primarily reflects its AC, or short time-scale, characteristics rather than previously well-studied DC characteristics such as saturation current, threshold voltage, and channel length. The circuit is implemented in an advanced CMOS SOI technology and occupies an area of 400μm × 20μm. Simulations show that the test circuit effectively isolates the possible presence of AC effects from known DC variation sources for the transistors.