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Thermal via structural design in three-dimensional integrated circuits | IEEE Conference Publication | IEEE Xplore

Thermal via structural design in three-dimensional integrated circuits

Publisher: IEEE

Abstract:

3D IC, a novel packaging technology, is heavily studied to realize improved performance with denser packaging and reduced wirelength. Despite numerous advantages, thermal...View more

Abstract:

3D IC, a novel packaging technology, is heavily studied to realize improved performance with denser packaging and reduced wirelength. Despite numerous advantages, thermal management is the biggest bottleneck to realize device stacking technology. In this paper, we propose a thermal-aware physical design for three-dimensional integrated circuits (3D IC). We aim to mitigate localized hotspots to ensure functionality by adding thermal fin geometry to existing thermal through silicon via (TTSV). We analyze various ways to insert thermal fin for single TTSV as well as TTSV cluster designs with the goal of maximizing heat dissipation while minimizing the interference with routing and area consumption. An analytical model of a three-dimensional system is developed and a thermal resistance circuit is built for accurate and time-efficient 3D thermal analysis.
Date of Conference: 19-21 March 2012
Date Added to IEEE Xplore: 19 April 2012
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ISSN Information:

Publisher: IEEE
Conference Location: Santa Clara, CA, USA

References

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