In this paper, we propose a novel analog circuit optimization methodology for achieving high parametric yield. We solve the statistical worst-case optimization problem by a sequence of linear programmings where performance metrics are fitted using sparse regression to take into account a large number of device-level parameters modeling process variations. In addition, we propose a margining mechanism to ensure accurate yield optimization with consideration of modeling errors. The efficacy of this method is demonstrated using two circuit examples where the cost function is minimized and high parametric yield (e.g., around 90%) is achieved compared to other conventional approaches.