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An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors | IEEE Conference Publication | IEEE Xplore

An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors


Abstract:

In this paper, we propose a novel compression method called Zero-Duplicate Compression (ZDC) to compress network traffic and to increase lifetime in Non-Volatile Memories...Show More

Abstract:

In this paper, we propose a novel compression method called Zero-Duplicate Compression (ZDC) to compress network traffic and to increase lifetime in Non-Volatile Memories (NVMs) as a Last-Level-Cache (LLC). Moreover, we limit compression by a new mechanism called Selective Compression Architecture (SCA) to reduce delay overhead and static energy from compression/decompression. Our experiments show that the ZDC provides comparable compression ratio to two other state-of-the-art compression methods and the SCA improves energy consumption and performance by about 76% and 11%, on average, compared with the traditional architecture, respectively.
Date of Conference: 14-15 March 2017
Date Added to IEEE Xplore: 04 May 2017
ISBN Information:
Print ISSN: 1948-3287
Conference Location: Santa Clara, CA, USA

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