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A 1GS/s 11b Time-Interleaved ADC in 0.13/spl mu/m CMOS | IEEE Conference Publication | IEEE Xplore

A 1GS/s 11b Time-Interleaved ADC in 0.13/spl mu/m CMOS

Publisher: IEEE

Abstract:

A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is scalable to high sampling rates is presented. This 1GS/S 11b ADC has 55dB pe...View more

Abstract:

A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is scalable to high sampling rates is presented. This 1GS/S 11b ADC has 55dB peak SNDR, consumes 250mW power, and occupies 3.5mm 2 area
Date of Conference: 06-09 February 2006
Date Added to IEEE Xplore: 18 September 2006
Print ISBN:1-4244-0079-1

ISSN Information:

Publisher: IEEE
Conference Location: San Francisco, CA, USA

References

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