Abstract:
A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is scalable to high sampling rates is presented. This 1GS/S 11b ADC has 55dB pe...View moreMetadata
Abstract:
A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is scalable to high sampling rates is presented. This 1GS/S 11b ADC has 55dB peak SNDR, consumes 250mW power, and occupies 3.5mm
2
area
Date of Conference: 06-09 February 2006
Date Added to IEEE Xplore: 18 September 2006
Print ISBN:1-4244-0079-1