In high-speed data link systems of over 40Gb/s, the data decision point in the CDR circuit is not often the optimum position of the eye diagram. The CDR circuit is fabricated using a 0.18 mum SiGe BiCMOS process. The f_t and f_max are 200 GHz and 180 GHz, respectively. To overcome a severe degradation of BER performance due to this misalignment, a 40 Gb/s CDR circuit integrated with an adaptive decision-point control scheme by using an eye-opening monitor feedback is developed. The key approaches are 40 Gb/s high-precision eye-opening monitor (EOM) circuit to detect an optimum decision point, an adaptive decision-point control (ADPC) scheme by using the EOM feedback, a decision- point adjustable self-aligned phase detector to achieve the ADPC operation. The combination of these approaches improves both the BER performance and the stability of CDR operation.