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A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU | IEEE Conference Publication | IEEE Xplore

A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU


Abstract:

Presently, cellular phones are used not only for voice communications or SMS, but also for video telephony, 3D Java gaming and high-end business applications. Adoption of...Show More

Abstract:

Presently, cellular phones are used not only for voice communications or SMS, but also for video telephony, 3D Java gaming and high-end business applications. Adoption of a High-Level- Operating System, such as SymbianOS or Linux in cellular phones is popular. A high-performance application processor serves as the host in such cellular phone systems and accompanies the baseband processor as a modem sub-system. Single-chip integration of an application processor and a baseband processor provides a good costperformance balance. Our 1st generation of a one-chip integration of an application and a baseband processor, SH-MobileG1 (G1), had 20 power domains for very low leakage current [1], and a 2nd generation, SH-MobileG2 (G2), incorporated a dynamic clock-stop scheme to reduce idle time power consumption [2]. SH-MobileG3 (G3) is the third generation of a single-chip application and baseband processor, with both low power consumption and good performance.
Date of Conference: 03-07 February 2008
Date Added to IEEE Xplore: 09 January 2009
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Conference Location: San Francisco, CA, USA

References

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