A 450ps access-time 512Kb SRAM macro is fabricated in a 45nm SOI technology [1]. The macro is adapted for use as the principal growable embedded-SRAM block in a 45nm ASIC library. We describe a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 58% reduction in read power consumption under constant voltage and frequency compared to the previous generation macro [2]. Also described is a single-device dynamic-leakage-suppression scheme that reduces total leakage power consumption by 37% with no wake-up-cycle requirements. Figure 21.2.1 shows the SRAM macro features.