CMOS technology has followed Moore's law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for future product applications. Despite the advances in process technologies and the resultant ability to produce ever-smaller feature sizes, the increasing variations of scaled devices in SRAM are playing an increasingly important role in determining the scaling of SRAM operating voltage (VCC), frequency and leakage power. We develop a high-performance voltage-scalable SRAM design in 32nm logic CMOS featuring 2^nd-generation high-κ metal-gate transistors and 4^th-generation strained silicon [1]. With the continued transistor performance enhancement and extensive process-circuit co-optimization, the 32nm SRAM design is able to achieve 2× improvement in density and 15% faster access speed when compared to the 45nm design [2] at the same voltage. The design supports a broad range of operating voltages to enable dynamic voltage scaling in today's high-performance and low-power applications. The design also features an integrated power management scheme with close-loop array leakage control, floating bitline and wordline driver sleep, resulting in 58% reduction of SRAM leakage consumption.