Low-power CMOS design has relied heavily on VDD scaling in the past to exploit the quadratic dependence of dynamic power and the exponential dependence of leakage power on voltage. Today, leading-edge low-voltage designs are pushing FET operation into the weak inversion and subthreshold regimes. Investigators around the world are reporting circuits at voltages between 180mV and 700mV that offer performance which could support a range of applications in wireless sensors, mobile phones, biomedical devices, and ultra-mobile PCs. However, these circuits are highly sensitive to variations in temperature and process. Ultra-low-voltage circuits will be increasingly challenging to design as feature sizes shrink. Current trends indicate nominal supply voltages are unlikely to be reduced much below 1V, transistor threshold voltages will likely remain between 0.3 and 0.4V to manage subthreshold leakage, and effects such as random- dopant fluctuation will increase the spread in transistor parameters, all of which create difficulties in designing robust circuits at low VDD. This Forum brings together leading experts to describe future challenges in ultra-low-voltage design, to explore ultra-low-voltage circuit techniques, and to stimulate thinking about prospects for future ultra-low-voltage high-volume products.