Abstract:
Digital-intensive PLL architectures emerge [1]–[4], exploiting the benefits of CMOS scaling. This work presents a digital-intensive, reconfigurable 86MHz–12GHz synthesize...Show MoreMetadata
Abstract:
Digital-intensive PLL architectures emerge [1]–[4], exploiting the benefits of CMOS scaling. This work presents a digital-intensive, reconfigurable 86MHz–12GHz synthesizer. Simple 2-step background calibration enables the use of an area- and energy-efficient 5ps TDC (0.01mm2 and 15-pJ per-shot). Static mismatch calibration lowers the DAC area 4 times. The PLL, featuring digital phase modulation is fully reconfigurable, with loop bandwidth ranging from 0.1–2MHz. At 7GHz, the 0.28mm2 PLL achieves −144dBc/Hz phase noise at 20MHz offset, for 0.56ps jitter in 40MHz bandwidth, consuming less than 30mW.
Date of Conference: 07-11 February 2010
Date Added to IEEE Xplore: 18 March 2010
ISBN Information: