F6: Signal and power integrity for SoCs | IEEE Conference Publication | IEEE Xplore

F6: Signal and power integrity for SoCs


Abstract:

This Forum is directed toward researchers and designers working in advanced technologies over the next 3-5 years. They will be required to solve emerging issues of signal...Show More

Abstract:

This Forum is directed toward researchers and designers working in advanced technologies over the next 3-5 years. They will be required to solve emerging issues of signal and power integrity in large, System-on-Chip applications which will raise issues of increasing difficulty. While struggling for higher performance, the designer must battle escalating noise and cross-talk. Interconnect delay and coupling will require new methods of routing and signal transmission. Supply-grid design will take increasing account of limited package and chip metalization through independent power domains, active and passive supply-noise cancellation, and voltage scaling. Increasingly- sensitive analog and RF circuit blocks must counter digital chip noise. Stringent clock-jitter and skew targets, and power-dissipation limitations will be addressed by independent clock domains, resonant clocking, and frequency scaling.
Date of Conference: 07-11 February 2010
Date Added to IEEE Xplore: 18 March 2010
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Conference Location: San Francisco, CA, USA

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