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A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS | IEEE Conference Publication | IEEE Xplore

A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS


Abstract:

Communication in the unlicensed frequency band around 60GHz requires a very fast ADC with low resolution. We present a four-way interleaved converter, of which one channe...Show More

Abstract:

Communication in the unlicensed frequency band around 60GHz requires a very fast ADC with low resolution. We present a four-way interleaved converter, of which one channel is shown in Fig. 16.3.1, for these requirements. Dynamic pipelined conversion enables low power quantization at high speed with low input capacitance but requires calibration. A folding front-end halves the required calibration effort.
Date of Conference: 07-11 February 2010
Date Added to IEEE Xplore: 18 March 2010
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Conference Location: San Francisco, CA, USA

References

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