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A 900MHz direct ΔΣ receiver in 65nm CMOS | IEEE Conference Publication | IEEE Xplore

A 900MHz direct ΔΣ receiver in 65nm CMOS


Abstract:

Wireless communications is moving towards higher data rates but also requiring dynamic scalability of signal bandwidths in LTE to allow more optimization opportunities at...Show More

Abstract:

Wireless communications is moving towards higher data rates but also requiring dynamic scalability of signal bandwidths in LTE to allow more optimization opportunities at the network level. At the same time consumer devices are providing multiple active radio connections simultaneously, resulting in an extremely hostile interference environment due to intra-device coupling. Especially the trade-off between off-chip, passive out-of-band filtering and linearity remains a major challenge in highly optimized FDD systems like WCDMA [1] or LTE. Local RF loops have been proposed to remove the highest blockers [2] but still most of the commercial receivers e.g. [3] are adopting conventional direct-conversion or low-IF architectures. Various sampling techniques [4] including the bandpass ΔΣ approach [5] have been presented as solutions for a software-defined radio (SDR). However, they cannot address the RF linearity issue, and especially ΔΣ converters suffer from limited dynamic range and in many cases also from excessive power consumption. In this paper, a direct-conversion ΔΣ receiver architecture is proposed that can improve out-of-band linearity with an RF feedback loop as well as providing 56dB of SNDR for the 9MHz LTE signal. The prototype is not specifically designed to meet the LTE specification but it provides a flexible architecture for receivers supporting variable bandwidths and it can relax the filtering requirements both in RF and analog baseband processing.
Date of Conference: 07-11 February 2010
Date Added to IEEE Xplore: 18 March 2010
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Conference Location: San Francisco, CA, USA

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