Abstract:
To overcome the challenges that CMOS process scaling has imposed on the design of switched-capacitor amplification circuits, designers must consider a growing number of d...Show MoreMetadata
Abstract:
To overcome the challenges that CMOS process scaling has imposed on the design of switched-capacitor amplification circuits, designers must consider a growing number of design tradeoffs and employ new circuit techniques in order to achieve required accuracies, often at a cost of added power and complexity. This amplification performance bottleneck has been highlighted in recent years by the disparity in achievable power efficiency between SAR ADCs versus ADC structures that require amplification [1]. In many analog and mixed-signal topics, a comparison like this doesn't even exist, simply because amplification is a necessity. Even SAR ADCs have their limitations, particularly at higher resolutions where matching and noise constraints begin to dominate capacitor sizing and comparator power requirements.
Published in: 2012 IEEE International Solid-State Circuits Conference
Date of Conference: 19-23 February 2012
Date Added to IEEE Xplore: 03 April 2012
ISBN Information: