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Jaguar: A next-generation low-power x86-64 core | IEEE Conference Publication | IEEE Xplore

Jaguar: A next-generation low-power x86-64 core


Abstract:

“Jaguar” (JG) is the codename for AMD's follow-on project to the low-power x86-64 core, codenamed “Bobcat” (BT). AMD's first 28nm × 86 processor, the 3.08mm2 JG core is d...Show More

Abstract:

“Jaguar” (JG) is the codename for AMD's follow-on project to the low-power x86-64 core, codenamed “Bobcat” (BT). AMD's first 28nm × 86 processor, the 3.08mm2 JG core is designed to support a wide range of applications from low-power tablets requiring sub-5W SoCs to client products up to 25W. Similar to BT, the JG core uses integrated power gating to provide a low-power state for SOC power optimization. A JG compute unit (CU) is constructed using 4 JG cores, four 0.5MB L2 cache modules and an L2 interface (Fig. 3.4.1). An initial SOC has one 26.2mm2 CU, but AMD's modular design approach allows for different SOC configurations.
Date of Conference: 17-21 February 2013
Date Added to IEEE Xplore: 28 March 2013
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Conference Location: San Francisco, CA, USA

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