Recent innovations in semiconductor processes have accelerated the transition from analog circuits to their digital counterparts, with digital PLLs (DPLLs) being an example of this trend [1]. All-digital or fully synthesizable approaches, which exploit the merits of advanced processes, suffer from poor noise performance and high power consumption [2]. On the other hand, hybrid approaches, which employ analog components such as digital-to-analog converters (DACs), digital-to-time converters, phase interpolators (PIs) and regulators, have the typical difficulties associated with analog circuits, such as low output resistance, small voltage headroom and large variation. In this paper, we propose a highly digital architecture for a DPLL - one which minimizes the design effort typically required for analog circuits. The power and area-consuming circuits in prior works are replaced by power and area-efficient circuits with competitive performance. For example, a conventional time-to-digital converter (TDC) usually occupies considerable chip area in order to maximize input dynamic range with precise resolution [1]. Instead, in this work, a time-windowed phase-to-digital converter using interpolated DCO phases as a phase reference is adopted. In addition, conventional synchronous counters in the feedback path drastically increase the power consumption. Furthermore, retiming of data from the TDC is unavoidable due to the meta-stability of the sampling flip-flops [1]. The proposed divider scheme, which is composed of a multi-modulus frequency divider and a dead-zone-free phase and frequency detector (PFD), eliminates the need for a synchronous counter and retiming circuits. A calibration-free ΔΣ modulator (DSM) noise canceller is also included.