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A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS | IEEE Conference Publication | IEEE Xplore

A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS


Abstract:

The signal integrity (SI) of double data rate (DDR) memory links is affected by signal reflections due to the multi-drop configuration of heavily loaded memory busses. Va...Show More

Abstract:

The signal integrity (SI) of double data rate (DDR) memory links is affected by signal reflections due to the multi-drop configuration of heavily loaded memory busses. Variable-impedance drivers, on-die termination (ODT), feed-forward equalization (FFE) and slew-rate (SR) control are typically implemented in DDR transmitters to address SI issues. In particular for multi-module, multi-rank configurations where speed throttling must be applied, SR control turns out to be most effective to combat reflections and crosstalk. Slewed signal edges reduce the spectral content above the bit rate frequency, whereas FFE dampens lower frequencies to compensate for channel loss, which may, however, be less of a problem at throttled data rates.
Date of Conference: 17-21 February 2013
Date Added to IEEE Xplore: 28 March 2013
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Conference Location: San Francisco, CA, USA

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