Abstract:
Recent research indicates that data-link transceivers running at or below 40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and t...Show MoreMetadata
Abstract:
Recent research indicates that data-link transceivers running at or below 40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and telecom systems require transceivers to operate at even higher data rates. For example, a 400Gb/s Ethernet system may need 8×50Gb/s PAM2 (NRZ) or PAM4 channels [2]. This paper introduces fully integrated solutions for NRZ and PAM4 transmitters. The 60Gb/s operating speed demonstrates sufficient bandwidth even for standards with coding overhead.
Published in: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Date of Conference: 09-13 February 2014
Date Added to IEEE Xplore: 06 March 2014
ISBN Information: