The steep growth of digital-content consumption and increasing reliance on wireless networks has resulted in emerging standards such as IEEE 802.11ac. By employing spatial diversity, Multi-user MIMO and high-density modulation (up to 256-QAM), 802.11ac MIMO radios can provide significantly increased throughput, link robustness, and range while maintaining backward-compatibilities with existing 802.11a/n WLAN [1]. However, wide signal bandwidth and high-density modulation lead to significant challenges in all aspects of RF transceiver design, compared to previous WLAN standards. This paper introduces a fully integrated 3-stream MIMO WLAN SoC that integrates all of the functions of an 802.11a/b/g/n/ac WLAN with a record over-the-air TCP/IP throughput of 1.1Gb/s. The 40nm CMOS SoC integrates dual-band (2.4GHz and 5GHz) RF transceivers, data converters, digital physical layer, media access controller, and a PCI Express Gen-2 interface. The RF transceiver employs an alldigital fractional-N PLL with a record Figure-of-Merit (FoM) of −244dB, a wideband low-impedance bias circuit that minimizes pre-PA driver memory effect for 80MHz signal bandwidth, a dual-band receiver with 3dB/4.3dB NF, and a 5^th-order Chebyshev low-pass filter with constant-Gm bias and pre-distorted filter coefficients to support up to 80MHz signal bandwidth.