Abstract:
Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM can be directly integrated on the interpo...Show MoreMetadata
Abstract:
Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM can be directly integrated on the interposer or host chip and communicate with the memory controller. However, there are many limitations, such as reliability and testability, in developing the technology. It is advantageous to adopt a logic-interface chip between the interposer and stacked-DRAM with thousands of TSV. The logic interface chip in the base level of high-bandwidth memory (HBM) decreases the CIO, repairs the chip-to-chip connection failure, and supports better testability and improves reliability.
Published in: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Date of Conference: 09-13 February 2014
Date Added to IEEE Xplore: 06 March 2014
ISBN Information: