We report the implementation of a continuous-time linear equalizer (CTLE) featuring a new technique to control the high-frequency gain peaking and to interface to current-summing stages usually implemented as interleaved slices for the linear analog superposition of the coefficients of decision-feedback equalizers (DFE). The circuits are implemented in 14nm FinFET SOI CMOS technology and are included ina prototype receiver targeted to 16Gb/s serial I/O links for multi-core microprocessors off-chip communication. The architecture is shown in Fig. 10.6.1. Power efficiency and compactness are among the primary goals of the study together with an equalization capability sufficient to recover at bit-error rate (BER) levels below 10⁻¹² data transmitted across smooth channels with losses in excess of 25dB at 8GHz.