Digital fractional-N PLLs are increasingly used in place of analog fractional-N PLLs as frequency synthesizers in wireless applications, because they avoid large analog loop filters and can tolerate device leakage and low supply voltages, which makes them better-suited to highly-scaled CMOS technology [1-6]. However, the phase noise and spurious tone performance of previously published digital PLLs is inferior to that of the best analog PLLs. This is because all fractional-N PLLs introduce quantization noise, and in prior digital PLLs this noise has higher power or spurious tones than in comparable analog PLLs. Digital PLLs based on ΔΣ frequency-to-digital conversion (FDC-PLLs) offer a potential solution to this problem in that their quantization noise ideally is equivalent to that of analog PLLs, but prior FDC-PLLs incorporate charge pumps and ADCs that have so far limited their performance and minimum supply voltages [7,8]. This paper presents an FDC-PLL that avoids these limitations by implementing the functionality of a charge pump and ADC with a simple dual-mode ring oscillator (DMRO) and digital logic. Also demonstrated is a new quantization noise cancellation (QNC) technique that relaxes the fundamental bandwidth versus quantization noise tradeoff inherent to most fractional-TV PLLs. The new techniques enable state-of-the-art spurious tone performance and very low phase noise with a lower power dissipation and supply voltage than previously published state-of-the-art PLLs in the same class shown in Fig. 25.1.6.