25.2 A 2.2GHz −242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture | IEEE Conference Publication | IEEE Xplore

25.2 A 2.2GHz −242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture


Abstract:

This paper presents an all-digital phase-locked loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Cla...Show More

Abstract:

This paper presents an all-digital phase-locked loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequency-locked loop (FLL). Implemented in 65nm CMOS technology, the proposed PLL reaches an in-band phase noise of -112dBc/Hz and an RMS jitter of 380fs at 2.2GHz oscillation frequency. An FOM of -242dB has been achieved with a power consumption of only 4.2 mW.
Date of Conference: 22-26 February 2015
Date Added to IEEE Xplore: 19 March 2015
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Conference Location: San Francisco, CA, USA

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