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2.2 A scalable 28GHz coupled-PLL in 65nm CMOS with single-wire synchronization for large-scale 5G mm-wave arrays | IEEE Conference Publication | IEEE Xplore

2.2 A scalable 28GHz coupled-PLL in 65nm CMOS with single-wire synchronization for large-scale 5G mm-wave arrays

Publisher: IEEE

Abstract:

Demonstrations of mm-Wave arrays with >50 elements in silicon has led to an interest in large-scale mm-Wave MIMO arrays for 5G networks, which promise substantial improve...View more

Abstract:

Demonstrations of mm-Wave arrays with >50 elements in silicon has led to an interest in large-scale mm-Wave MIMO arrays for 5G networks, which promise substantial improvements in network capacity [1,2]. Practical considerations result in such arrays being developed with a tiled approach, where N unit cells with M elements each are tiled to achieve large MIMO/phased arrays with NM elements [2]. Achieving stringent phase-noise specifications and scalable LO distribution to maintain phase coherence across different unit cell ICs/PCBs are a critical challenge. In this paper, we demonstrate a scalable, single-wire-synchronization architecture and circuits for mm-Wave arrays that preserve the simplicity of daisy-chained LO distribution, compensate for phase offset due to interconnects, and provide phase-noise improvement with increasing number of PLLs [3]. Measurements on a scalable 28GHz prototype demonstrate a 21% improvement in rms jitter and a 3.4dB improvement in phase noise at 10MHz offset when coupling 28GHz PLLs across three different ICs.
Date of Conference: 31 January 2016 - 04 February 2016
Date Added to IEEE Xplore: 25 February 2016
ISBN Information:
Electronic ISSN: 2376-8606
Publisher: IEEE
Conference Location: San Francisco, CA, USA

References

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