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4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performance | IEEE Conference Publication | IEEE Xplore

4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performance


Abstract:

Intel's 6th generation Core processor (code named “Skylake” or SKL) was designed to enable PC performance and user-experience at smaller and thinner form factors and enab...Show More

Abstract:

Intel's 6th generation Core processor (code named “Skylake” or SKL) was designed to enable PC performance and user-experience at smaller and thinner form factors and enable fan-less PC platforms. It required optimization to an extremely low thermal design point (TDP). The lower average power consumption of SKL vs. the previous generation considerably increases the system battery life and allows full-day battery life or thinner designs with smaller batteries. The SKL product family is manufactured using an Intel 14nm tri-gate CMOS 11-metal-layer technology, as with the previous Core generation. Different dice include: 2 or 4 cores, a shared last-level cache (LLC, 1MB/core), a scalable graphic processor (GP) with 24, 48 or 72 execution units (EU), an image processing unit (IPU, supporting 4 cameras simultaneously), 2 channels of DDR3/LPDDR3/DDR4, a display engine (DE) and 3 display IO ports configurable to eDP, DP or HDMI. In mobile SKUs, the peripheral control hub (PCH) resides in the same package (MCP) as the CPU and communicates through an on-package IO (OPIO) bus. For desktop (DT), the PCH resides on the platform. Fig. 4.1.1 presents the SKL block diagram for the minimum configuration (2 cores, 24 EU GP, MCP). A key challenge was the need to add new capabilities, while reducing power, especially for some of the popular uses (media, casual gaming, speech recognition and advanced imaging).
Date of Conference: 31 January 2016 - 04 February 2016
Date Added to IEEE Xplore: 25 February 2016
ISBN Information:
Electronic ISSN: 2376-8606
Conference Location: San Francisco, CA, USA

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