In the past several years, CMOS image sensors (CISs) with sub-single-electron noise level, particularly, deep sub-electron read noise (less than 0.5e-rms), have been reported. Such an ultra-low noise level is realized with a reduced floating diffusion (FD) node capacitance for attaining the high pixel conversion gain (CG) [1,2], and a high-gain readout circuitry with noise-reduction capabilities [3,4]. Recently, a reset-gate-less (RGL) CMOS image sensor has been reported [5]. It shows an excellent read noise performance using an optimized pixel structure for high CG and high-gain column ADC with multiple sampling. In this technique, however, a very high pulsed voltage of approximately 25V for the FD reset is essential to cause a punch-through effect. It is not suitable for image sensors with high pixel resolution and high-speed signal readout. This paper presents a low read noise 0.5Mpixel RGL-pixel CMOS image sensor at 32Hz sensor operation with a bootstrapping reset method. The CIS does not have a reset gate (RG) to eliminate the parasitic coupling capacitance between RG and FD, as in [5], but the FD reset is done by a capacitive coupling between the FD and the source follower output. This technique, named “bootstrapping reset,” does not need a high supply voltage for FD resetting, and high-speed rowby-row resetting is realized while achieving raster-scan readout.