This session describes state-of-the-art transmitter and PA designs implemented in deep-submicron CMOS processes featuring low noise, wide bandwidth, and high efficiency. It includes a multi-mode front-end Module with CMOS PA for GSM/EDGE/TD-SCDMA/TD-LTE application, a 14nm SAW-less transmitter with a voltage-mode harmonic-reject mixer, a 28nm multilevel outphasing transmitter enabling 400MHz instantaneous bandwidth, a 28nm digital polar transmitter supporting 40MHz LTE Carrier Aggregation (CA), a 28.6dBm CMOS digital PA with 35% PAE, a 24dBm digital PA with built-in AM-PM distortion self-compensation and several digital PA/transmitter designs for cellular, 802.11, IoT, and wearable applications.