Abstract:
The Internet-of-Things (IoT) is gaining momentum, and the ultra-low-power (ULP) RF transceiver is one of the key enablers. Generation of the local oscillator (LO) consume...Show MoreMetadata
Abstract:
The Internet-of-Things (IoT) is gaining momentum, and the ultra-low-power (ULP) RF transceiver is one of the key enablers. Generation of the local oscillator (LO) consumes a significant share of the total energy of these ULP transceivers which are typically powered by small batteries. Therefore, a fractional-N PLL needs to perform LO frequency synthesis and modulation with a very stringent power budget, i.e., below 1mW [1]. A digital PLL is favored in these applications because of the benefit of small area, which is also a critical cost consideration in IoT. On the other hand, the LO quality generated by these ULP PLLs cannot be compromised, and it needs to fulfil the RF requirements defined in the IoT standards, e.g., Bluetooth Low Energy (BLE). Although the integrated phase error is less stringent in IoT standards, the spectral purity requirements remain critical in order to fulfill the regional spectrum regulations, e.g., FCC. A high fractional spur level due to the non-linearity in PLLs (e.g., from a TDC) introduces the unwanted emission. In this work, we present a ULP dividerless digital PLL with a power-efficient spur-mitigation technique. Furthermore, one of the critical issues of the dividerless (or sub-sampling) PLLs, the lack of frequency capture capability without the assistance of an extra power-hungry frequency-locked-loop (FLL), is addressed and mitigated by the proposed digital phase unwrap technique.
Date of Conference: 05-09 February 2017
Date Added to IEEE Xplore: 06 March 2017
ISBN Information:
Electronic ISSN: 2376-8606