A clock generator using an injection-locked oscillator (ILO) offers remarkable jitter performance with low-overhead of additional circuits such as injection switches. Because the injection clock cleans the edge of the oscillator in every injection period, jitter accumulation is avoided. However, the ILO alone causes a severe reference spur owing to the mismatch between the desired oscillation frequency set by the injected reference and the free-running frequency that could change over the process, supply voltage, and temperature (PVT) variations. For this reason, continuously tuning the free-running oscillation frequency, F_OSC, to nullify the frequency error, F_ERR, is required. Here F_ERR is the frequency difference between F_OSC and the multiplication ratio, N, times the reference frequency, F_REF. For minimizing such performance degradations, techniques such as pulse gating and replica-delay cells have been presented. While the minimization of F_ERR is achieved, the path delay mismatch between the injection and the phase detector remains unsolved, limiting the spur reduction capability. Thus, a precise calibration for equalizing the delay mismatch is required for achieving low spur performance. This paper proposes an injection-locked all-digital phase-locked loop (IL-ADPLL) with a time-division dual calibration (TDDC) scheme for reducing the reference spur with robust performance against PVT variations.