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A 1.1mW 200kS/s incremental ΔΣ ADC with a DR of 91.5dB using integrator slicing for dynamic power reduction | IEEE Conference Publication | IEEE Xplore

A 1.1mW 200kS/s incremental ΔΣ ADC with a DR of 91.5dB using integrator slicing for dynamic power reduction


Abstract:

Nyquist-rate ADCs with high resolution are needed in many applications where, for example, multiplexed operation is needed as for multichannel sensor readout. For various...Show More

Abstract:

Nyquist-rate ADCs with high resolution are needed in many applications where, for example, multiplexed operation is needed as for multichannel sensor readout. For various tasks such as averaging-based analysis or lock-in detection high linearity at the presence of very low noise is required. While SAR ADCs are known for high power efficiency, they often show limited effective resolutions and linearity unless oversampling, mismatch error shaping or calibration techniques are employed [1,2]. The state of the art in high-resolution ADC design is thus dominated by oversampled converters, and for Nyquist-rate operation a significant power penalty must be paid.
Date of Conference: 11-15 February 2018
Date Added to IEEE Xplore: 12 March 2018
ISBN Information:
Electronic ISSN: 2376-8606
Conference Location: San Francisco, CA, USA

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