For Class-D audio amplifiers, the closed-loop topology formed by a loop filter, a pulse-width-modulation (PWM) modulator and a switching power stage is commonly adopted since it effectively suppresses the power-stage nonlinearity to improve total harmonic distortion plus noise (THD+N). However, unless a higher switching frequency (fSW) or a higher-order loop filter is adopted [2]-[4], the PWM-residual-aliasing distortion [1] introduced by the feedback loop limits the minimum THD+N. This leads to a tradeoff between THD+N and quiescent current (IQ). Moreover, since typical audio signals have a high crest factor of 10 to 20dB [1], the IQ of audio amplifiers in battery-powered applications should be minimized to extend the battery usage time. To achieve both low THD+N and low IQ, the PWM-residual-aliasing reduction methods presented in [1] and [5] reduce the PWM-residual-aliasing distortion for 2^nd-order Class-D amplifiers without increasing the fSW, thereby preventing an increase in the switching power loss. However, the replicated loop filter in [5] requires additional static current; while in [1], the inherent phase-shift delay between the loop filter output and the input signal limits the effectiveness of PWM residual cancellation, leading to degraded THD+N.