This paper describes a new CPU subsystem featured in a 5G mobile SoC. The High-Performance (HP) core achieves a 3GHz clock frequency with full production yield across the fabrication range and operating environment. In contrast to previously published work [1], a third, balanced-performance (BP), gear is introduced which features a power-optimized implementation of the high-performance (HP) core. Physical implementation differences of the BP and HP cores are illustrated, while circuit techniques developed to enable full-yield 3GHz operation are detailed. A die photograph alongside a more detailed HP core CAD drawing are shown in Fig. 4.1.7 and the cluster topology, including architectural features, is summarized in Fig. 4.1.1.