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33.9 A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend | IEEE Conference Publication | IEEE Xplore

33.9 A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend


Abstract:

Neural interface implants are revolutionizing neuroscience research, especially in brain-machine interfaces and neuromodulation therapies. Miniaturizing implants can sign...Show More

Abstract:

Neural interface implants are revolutionizing neuroscience research, especially in brain-machine interfaces and neuromodulation therapies. Miniaturizing implants can significantly reduce their invasiveness and prevent them from impeding natural behaviors due to size or tethering. However, device miniaturization brings new challenges when the implant needs to support power-intensive applications like optical stimulation. These challenges arise from the power Rx (e.g., a coil) receiving a limited amount of power due to its small size. Hence, the recently demonstrated miniature implants can only support a single neural interface modality, either stimulation or neural recording [1–4]. To bridge this gap, we designed a miniature neural interface implant for simultaneous optical stimulation and neural recording. The ASIC of the implant incorporates a linear charging switched capacitor stimulation (LC-SCS) structure that can deliver peak pulses of 12mA to the LED with 95% charging efficiency while reducing the off-chip components required by the ASIC to one small capacitor. This innovation facilitates both device miniaturization and wireless power transmission. The ASIC also employs an artifact-tolerant frontend design, in which a CT-\Delta \Sigma \mathrm{M} directly digitizes neural signals with a peak SNDR of 81.9dB and a dynamic range (DR) of 83.7dB. This innovative frontend ensures reliable neural recording, even in the presence of artifacts up to 400mV_{PP}.
Date of Conference: 18-22 February 2024
Date Added to IEEE Xplore: 13 March 2024
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Conference Location: San Francisco, CA, USA

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