Abstract:
This paper analyzes high-speed source-synchronous network-on-chip data links in terms of yield loss due to delay variations. We show that statistical process variations c...Show MoreMetadata
Abstract:
This paper analyzes high-speed source-synchronous network-on-chip data links in terms of yield loss due to delay variations. We show that statistical process variations can significantly reduce yield at high data rates and high bus widths. An on-chip delay calibration architecture for individual calibration of rise and fall delay times is proposed and analyzed on system level using Monte Carlo simulations. A sizing strategy for compensation delay elements is derived for yield maximization with low effort in terms of chip area and energy consumption.
Published in: 2010 International Symposium on System on Chip
Date of Conference: 29-30 September 2010
Date Added to IEEE Xplore: 09 November 2010
ISBN Information: