Efficient compensation of delay variations in high-speed network-on-chip data links | IEEE Conference Publication | IEEE Xplore

Efficient compensation of delay variations in high-speed network-on-chip data links


Abstract:

This paper analyzes high-speed source-synchronous network-on-chip data links in terms of yield loss due to delay variations. We show that statistical process variations c...Show More

Abstract:

This paper analyzes high-speed source-synchronous network-on-chip data links in terms of yield loss due to delay variations. We show that statistical process variations can significantly reduce yield at high data rates and high bus widths. An on-chip delay calibration architecture for individual calibration of rise and fall delay times is proposed and analyzed on system level using Monte Carlo simulations. A sizing strategy for compensation delay elements is derived for yield maximization with low effort in terms of chip area and energy consumption.
Date of Conference: 29-30 September 2010
Date Added to IEEE Xplore: 09 November 2010
ISBN Information:
Conference Location: Tampere, Finland

References

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